A Low Power Viterbi Decoder for Trellis Coded Modulation System
نویسنده
چکیده
Forward Error Correction (FEC) schemes are an essential component of wireless communication systems. Convolutional codes are employed to implement FEC but the complexity of corresponding decoders increases exponentially according to the constraint length. Present wireless standards such as Third generation (3G) systems, GSM, 802.11A, 802.16 utilize some configuration of convolutional coding. Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. Viterbi algorithm is the most extensively employed decoding algorithm for convolutional codes. The main aim of this project is to design FPGA based Viterbi algorithm which encrypts / decrypts the data. In this project the encryption / decryption algorithm is designed and programmed in to the FPGA.
منابع مشابه
Fpga Implementation of High Speed and Low Power Viterbi Encoder and Decoder
AbstractImplementation of the viterbi decoder in the FPGA plays a dominant role for power and high speed mechanisms. The viterbi decoder is the most efficient decoder. It is commonly used in a wide range of communication and data storage applications. It uses trellis coded modulation (TCM) technique to find the trellis path in the circuit. Here, pre-computation techniques have been adopted for ...
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متن کاملIJSRD - International Journal for Scientific Research & Development| Vol. 2, Issue 08, 2014 | ISSN (online): 2321-0613
It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a precomputation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading t...
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